/*
 * Copyright (c) 2020-2021, SERI Development Team
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Change Logs:
 * Date           Author       Notes
 * 2022-05-22     Lyons        first version
 */

module pa_fpu_xfrac_post_shift_left (
    expn_adjust_i,
    xfrac_rnd_i,
    xfrac_rnd_o
    );

//width of xfrac_rnd is 57-bits
//include: hidden:1 + frac:52 + grs:3

input               expn_adjust_i;
input               xfrac_rnd_i;
output              xfrac_rnd_o;

wire [2:0]          expn_adjust_i;
wire [56:0]         xfrac_rnd_i;
wire [56:0]         xfrac_rnd_o;


reg  [56:0]         xfrac_rnd_out;

wire [2:0]          shift_cnt;
wire [56:0]         shift_pre_data;


assign shift_cnt[2:0] = expn_adjust_i[2:0];
assign shift_pre_data[56:0] = xfrac_rnd_i[56:0];

always @ (shift_cnt[2:0] or shift_pre_data[56:0]) begin
case (shift_cnt[2:0])
    3'b000 : xfrac_rnd_out[56:0] =  shift_pre_data[56:0];
    3'b001 : xfrac_rnd_out[56:0] = {shift_pre_data[55:0], 1'b0};
    3'b010 : xfrac_rnd_out[56:0] = {shift_pre_data[54:0], 2'b0};
    3'b100 : xfrac_rnd_out[56:0] = {shift_pre_data[53:0], 3'b0};
    default :
             xfrac_rnd_out[56:0] = {57{1'bx}};
endcase
end

assign xfrac_rnd_o[56:0] = xfrac_rnd_out[56:0];

endmodule